A conventional synchronization circuit synchronizes an asynchronously inputted signal with a synchronization clock, and outputs the synchronized signal (refer to Japanese Published Patent Application No. 5-327676 and USP4965814). Hereinafter, the conventional synchronization circuit will be described with reference to FIG. 17.
FIG. 17 is a block diagram illustrating the construction of the conventional synchronization circuit.
With reference to FIG. 17, a flip-flop 1 receives an input signal SIN that is asynchronous to a synchronization clock SCK and an inverse clock nSCK that is output from an inverter 5, and the flip-flop 1 latches the input signal SIN at a timing of a rising edge of the inverse clock nSCK. A flip-flop 2 receives the input signal SIN and the synchronization clock SCK, and latches the input signal SIN at a timing of a rising edge of the synchronization clock SCK. A flip-flop 3 receives a signal that is selected by a selection circuit 4 and the synchronization clock SCK, and outputs a synchronizing signal SOUT at a timing of the rising edge of the synchronization clock SCK. The selection circuit 4 selects either the output of the flip-flop 1 or the output of the flip-flop 2 based on a control signal CTL that is output from a switching control circuit 6. The inverter 5 receives the synchronization clock SCK, and outputs the an inverse clock nSCK that is obtained by inverting the synchronization clock SCK. The switching control circuit 6 outputs a control signal CTL according to the temporal relationship between a transition point of the input signal SIN and an edge of the synchronization clock SCK.
Hereinafter, the operation of the conventional synchronization circuit as constructed in the manner as described above with reference to FIG. 17 will be described.
The asynchronous input signal SIN is applied to respective data terminals D of the flip-flops 1 and 2.
When the inverse clock nSCK that is outputted from the inverter 5 is input to the flip-flop 1 through a clock input terminal CK, the flip-flop 1 latches the input signal SIN at a timing of the rising edge of the inverse clock nSCK, and outputs the signal to the selection circuit 4 through a data output terminal Q.
Further, when the synchronization clock SCK is input to the flip-flop 2 through a clock input terminal CK, the flip-flop 2 latches the input signal SIN at a timing of the rising edge of the synchronization clock SCK, and outputs the signal to the selection circuit 4 through a data output terminal Q.
On the other hand, the switching control circuit 6 monitors the temporal relationship between the transition point of the asynchronous input signal SIN and the edge of the synchronization clock SCK, and outputs the control signal CTL when detecting that the temporal relationship approaches a predetermined period of time, to thereby control the selection circuit 4.
The flip-flop 3 latches the signal that is selected by the selection circuit 4 at a timing of the rising edge of the synchronization clock SCK, and outputs a synchronizing signal SOUT through a data output terminal Q.
In this way, the asynchronous input signal SIN is synchronized with the synchronization clock SCK.
However, the signal which is latched at the inverse clock nSCK has already been output from the selection circuit 4 when the switching control circuit 6 detects that the transition point of the asynchronous input signal SIN approaches the edge of the synchronous clock SCK, and this signal is again latched at the synchronization clock SCK by the third flip-flop 3, and as a result, a latency is undesirably added to the signal.
Furthermore, there are many cases where plural pieces of asynchronous signals are input in recent multi-channel digital transmission, and skews between the plural input signals adversely affect data transmission as the input signals become faster. Since, in the conventional technique, there is a possibility that a latency is added to each inputted signal, such skews cause a serious problem in data transmission in which error-free signal synchronization should be carried out.